Option ro

Enabling software write protect and specifying the RO region as the protected range Background The core of the Chrome OS security model is rooted in a firmware image that we fully control and whose integrity we can guarantee.

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All existing designs have accomplished this through a dedicated flash part which is guaranteed to be read-only once the device is shipped to customers. The point is that the entire system security hinges upon the integrity of the RO firmware. This is a physical line to the flash where the RO firmware is stored that tells the flash chip to mark some parts as read-only and to reject any modification requests. So even if Chrome OS was full of bugs and was exploited to gain all the permissions for direct write access to all pieces of hardware in the system, any RO firmware write attempts from code running on the CPU would be stopped by the option ro chip itself.

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Then when the system reboots, the verified boot process would detect any modifications or corruption to the hard drive e. Thus we can confidently tell customers: if you can reboot a Chromebook into the login screen, you know it's secure.

This is a somewhat tricky topic since write protection implementations can differ option ro chips option ro the hardware write protection has changed over time. Our security goals have been that, in order to disable flash WP, someone needs extended physical access to the device, and it would take a non-trivial amount of effort and time to open up the device in order to remove the WP screw and thus disable the WP signal making the RO firmware writable from software. In newer devices, we've moved away from the WP signal being controlled by a physical screw and to a separate option ro controlling the WP signal.

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That way we have more flexible control over the WP signal. It still takes long time and physical presence to diable write protection, and can be configured such that only the device owners are authorized to disable write protection.

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That separate chip is option ro referred to as a secure element SEthe firmware controlling the SE is called Cr This secure element firmware is fully authored and controlled by Google.

Note that even in case of the devices protected by the SE, opening option ro the device and disconnecting the battery would still disable write protection.

Software write protect In addition to the hardware WP signal, there is a software WP setting that allows us some more flexibility in bitcoin zu dollar rate write protection. The Block Protect, BP, bits mask the regions within the SPI flash data address space such that access that results in option ro can be controlled.

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This allows us to ship systems with hardware WP on, but leaving software WP off until a point in time where software decided to engage it. One case where we're using this is devices that originally get flashed with development signing keys, but option ro get upgraded to production keys, after which option ro WP would get enabled.

Since the start of the project, the Chrome OS team strongly believes that when someone buys a device, they own it fully. To that end, we strongly believe that users must be free to fully program their device in any way they want.


option ro Developer mode and support for developers and free software is extremely important to us as a project. So if someone wanted to write their own firmware which they can as the firmware on devices is open source that we releasethey should have that ability.

The ability to reprogram firmware is also a core requirement for Google-internal development needs.

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It would option ro much more complicated during the early phases of a new hardware project to iron out kinks without the ability to fix firmware on the chips in the devices themselves. This pin is asserted through various physical means, but with effort, users can unprotect devices they own.

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While this pin is asserted, certain debug features eg. Option ro Write Protection Status All commands shown in this section are ran on the Chrome OS device terminal, which is available when the device is booted in developer mode. Software Write Protection and Write Protection Range Status To check software write protection and write protection range status, run the following commands.

Note that the write protection range is independent from the software write protection status if sw write protection is disabled, it means you can manipulate the protection range. Disabling hardware write protect Power down the device and open the case Locate and remove the write protect screw on the motherboard.

Connect to that console with minicom, cu, or screen. Run wp disable on the Cr50 console. Disassemble the device, locate the battery connector, remove the battery connector from the PCB to disconnect the battery. Reassemble the device, insert the original OEM charger necessary since the option ro is no longer providing power to the systemthen boot to developer mode.

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Servo Header Servo when connected can override the native write protection either using the write protect screw or the security element. Disabling software write protect NOTE: You cannot disable software write protect if hardware write protect is enabled.

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Run flashrom -p host --wp-disable. Run flashrom -p ec --wp-disable.

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  • Chromium OS Docs - Write Protection

Do an EC Reset. Enabling write protect Hardware write protect can be controlled by 3 different mechanisms: A write-protect screw, when present, Cr50 firmware, when present, and A pin option ro the servo header, option ro servo is connected Write Protect Screw For systems with a write-protect screw: Power down the device and open the case Insert the write protect screw on the motherboard.

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  • Network File System (NFS)

This command will fail if factory mode is not enabled. Newer Chrome OS versions allow to enable flash write protection by running gsctool -a --wp enable See also the internal crosops docs. Or you can control it with a suzyQ: Connect to Cr50 console with a serial terminal program minicom, cu, screen, etc.

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